The Open Systems Interconnections model (OSI model) is a product of the Open Systems Interconnection effort at the International Organization for Standardization. The OSI model subdivides communication systems into parts called “layers”, each of which performs a collection of conceptually similar functions that provide services to a layer above it and which receives services from a layer below it. On each layer, an “instance” provides services to the instances at a layer above it and requests services from a layer below it.
The OSI model has two major components: an abstract model of networking known as the “Basic Reference Model” or “seven-layer model” and a set of specific protocols. Protocols enable an entity in one host to interact with a corresponding entity at the same layer in another host.
The first three layers under the seven-layer model are referred to as the “media layers.” The remaining four layers are known as the “host layers.” More particularly, layer 1 is the physical (“PHY”) layer, layer 2 is the data link (“LINK” or, sometimes, “MAC”) layer, layer 3 is the network layer, layer 4 is the transport layer, layer 5 is the session layer, layer 6 is the presentation layer and layer 7 is the application layer.
The PHY layer connects a LINK layer device to a physical medium such as an optical fiber or copper cable. The PHY layer is often the most complex part of the communication system and defines the electrical and physical specifications for devices. In particular, the PHY layer defines the relationship between a device and a transmission medium, such as a copper or optical cable. This includes the layout of pins, voltages, cable specifications, hubs, repeaters, network adapters, host bus adapters (HBA used in storage area networks) and more.
The major functions and services performed by the PHY layer include: 1) the establishment and termination of a connection to a communications medium; 2) participation in the process whereby communication resources are shared; and 3) modulation or conversion between digital data in user equipment and the corresponding signals transmitted over a communication network.
PHY layers are present in many interface technologies such as Wi-Fi, Ethernet, USB, IrDA, SATA, SDRAM and flash memory interfaces. For example, a PHY chip is integrated into most Universal Serial Bus (USB) controllers in hosts or embedded systems and provides the bridge between the digital and modulated parts of the interface.
FIG. 1 illustrates a LINK layer circuit SOC 10 and a PHY layer circuit ULPI PHY 12 of, for example, a USB interface. Circuits 10 and 12 communicate, in this example, using the Ultra Low Pin-count Interface (“ULPI”) specification. The acronym “SOC” stands for “System On Chip.”
SOC 10 includes link logic 14, ULPI Link Wrapper 16 and a UART 18, all of which are coupled to a processor bus 20. Link logic 14 is coupled to ULPI Link Wrapper by a 56 line UTMI+ bus 22 and UART 18 is coupled to ULPI Link Wrapper 16 by a line 24.
ULPI PHY 12 includes ULPI PHY Wrapper logic 26 and a UTMI+ PHY 28 which are coupled together by a UTMI+ bus 30. A PHY frequency reference 32 is coupled to UTMI+ PHY 28. The output of UTMI+ PHY 28 includes VBUS, D+, D−, ID and GND, in this example. The ULPI Link Wrapper is also coupled directly to the processor bus 20.
The ULPI specification calls for 12 pins or lines to connect the SOC 10 and the ULPI PHY 12. These 12 pins include a STP line 34, a clk (60 MHz) line 36, an eight-bit data bus 38 (“Data [7:0]”), a DIR line 40 and a NXT line 42. The ULPI Link Wrapper 16 communicates with the ULPI PHY Wrapper 26 using these 12 lines or pins.
FIG. 2 illustrates SLPI circuitry 44 designed to implement a new PHY specification known as the Serial Link Peripheral Interface (“SLPI”), which has been under development for the past few years. The Serial Link PHY Interface (SLPI) Specification, incorporated herein by reference, was published on Sep. 10, 2010 as Revision 0.82t. A release Revision 9.0 is expected by December 2010.
With continuing reference to FIG. 2, SLPI circuitry 44 includes an SOC circuit 46 and a PHY circuit 48. The front end of SOC circuit 46 can be of similar design to the SOC 10 of FIG. 1, where like reference numerals correspond to like elements. The back end of SOC circuit 46, however, includes a SLPI Bridge 50 which has differential outputs slpi_dp and slpi_dn which conform to the new SLPI standards. Bridge 50 includes a bridge core 52, a differential transmitter 54, two differential receivers 56 and 56, an Idle/Hold circuit 60 and two termination resistors 62 and 64.
PHY circuit 48 includes a PHY core 66, a differential transmitter 68, two differential receivers 70 and 72, an Idle/Hold circuit 74 and two termination resistors 76 and 78. The PHY circuit 48 also includes a PHY Timer 80, a differential transmitter 82 and a differential receiver 84. The output of PHY circuit 48 includes the same pins or lines as the UTMI+ PHY 28 of FIG. 1, namely VBUS, D+, D−, ID and GND, in this example.
The SLPI specification will provide a communication system having a number of improvements over that of the ULPI specification including: 1) a lower number of input wires (two with SLPI versus twelve with ULPI); 2) single ended signaling (SLPI is fully differential and terminated, resulting in lower emissions, improved immunity and longer traces); 3) lower power (e.g. SLPI my use 500 μA v. 15 mA with ULPI); 4) less timing restraints (SLPI has independent clock references for PHY and LINK); 5) a smaller footprint (SLPI can be, for example, 4×4 WLP while ULPI cannot be smaller than 5×5 WLP); and 6) native support for Link-2-Link communication.
Due to the many advantages of SLPI over ULPI it is expected that SLPI will eventually replace ULPI for most applications in the coming years. However, the new SLPI specification requires both a new protocol and new electrical bus (2 wires, fully differential, dynamically terminated) which cannot be derived from any of the existing differential interfaces, such as Low Voltage Differential Signaling (“LVDS”) or Reduced Swing Differential Signaling (“RSDS”) used in conjunction with the ULPI specification. This is unfortunate, in that is it relatively easy to connect, for example, Field Programmable Gate Arrays (“FPGAs”) as LINK circuits implementing ULPI protocols using General Purpose Input/Outputs (“GPIOs”), none of which can be adapted to be compatible with the SLPI electrical bus specification. In consequence, FPGAs or Application Specific Integrated Circuits (ASICs) equipped with GPIO/LVDS/RSDS I/Os won't be able to communicate with a SLPI PHY.
It typically takes a number of years for a new standard to be adopted. In the case of the SLPI specification, it is anticipated that SLPI PHYs will become available, due to their many advantages as set forth above, before the LINK-side FPGAs and ASICs are modified to accommodate the new SLPI electrical standard.
These and other limitations of the prior art will become apparent to those of skill in the art upon a reading of the following descriptions and a study of the several figures of the drawing.